1. Field of the Invention
The present invention generally relates to data transfer within a computing environment and, more particularly, to cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers.
2. Description of the Related Art
In modern computing environments, multiple devices are oftentimes interconnected to provide processing speed and flexibility within the computing environment. In such architectures, data exchanged between the interconnected devices is susceptible to corruption due to intermittent noise or other interruptions during transmission of the data from the source device to the receiving device. To detect such corruption, some computing environments employ a technique whereby a calculation is performed on the data to be transmitted, and the result of the calculation is transmitted by the source device along with the data. The receiving device performs the same calculation on the data when received and compares the value calculated by the receiving device with the transmitted value calculated by the source device. The two calculations being identical indicates that the data has been transmitted successfully. The two calculations being different indicates that the data has been corrupted, thereby causing the receiving device sends a request to the source device to retransmit the data packet.
One such technique is known as a cyclic redundancy check (CRC). Using the CRC technique, the source device and receiving device perform a function on the transmitted data that resembles long division. The result of the function is transmitted by the source device as a check value along with the data, and the receiving device compares the received check value with the computed check value. The check value is typically computed by using a linear feedback shift register (LFSR). LFSR circuits are relatively easy to implement in hardware, and reliably detect corruptions in transmitted data.
As computing environments have evolved, data is transmitted over channels using more binary digits (bits) per data word. LFSR designs increase in complexity and physical size as a function of the number of bits per data word. As a result, the LFSR circuit consumes more space as the number of bits per data word increases. In one example, the number of bits per data word defined by PCI Express™ (PCIe) 3.0 has doubled as compared to PCIe 2.0, while the hardware surface area for the LFSR to implement CRC has increased 3.6 times in size.
In addition to this problem, some communication protocols define multiple CRC values to be computed by a source device and receiving device, resulting in multiple LFSR circuits for each source device and receiving device. Complex devices may have multiple source devices and receiving devices, each needing one or more LFSR circuits to implement CRC. Thus, computing devices need larger and multiple LFSR circuits to ensure reliable data transmission. As a result, a significant portion of the surface area and the power consumed on an integrated circuit that implements a source device or receiving device are associated with LFSR circuits.
As the foregoing illustrates, what is needed in the art is a more efficient technique to ensure reliable data transfers within a computing environment.